Successful execution of IC functions relies on both the memory and logic operating as intended. If a memory cell, latch, or flip-flop is upset (i.e., flipped from one digital state value to the opposite digital state value), such as by a cosmic ray, heavy ion, or electronic noise, the result is an error in the functionality of the IC that is commonly referred to as a “soft error”.
For critical applications, where a soft error might result in a catastrophic failure, XILINX, INC., of San Jose, Calif., has developed techniques and tools commonly referred to as “triple modular redundancy” (“TMR”). TMR basically uses three versions of a circuit, operates the circuits in parallel, and compares the three outputs. If all three outputs are the same, that output value is accepted. If only two of the outputs are the same, the assumption made is that the third output arose because of a soft error in either the memory or logic of that circuit. The value used is the common value between the two outputs, and the uncommon value is basically discarded (although error logging may optionally be performed).
Tools have been developed to implement TMR in configurable ICs, such as field-programmable gate arrays (“FPGAs”). A typical TMR tool creates functionally correct logic in electronic design interchange format (“EDIF”) suitable for use with automatic place and route tools. An automatic place and route tool selects the physical resources of the FPGA that will make up the triple redundant circuits and produces a configuration file (data stream), that, when programmed into the FPGA, configures the FPGA for the intended application.
While TMR techniques are highly valuable for real-time soft error mitigation, such techniques consume substantial on-chip resources. Therefore, soft error mitigation techniques that consume less on-chip resources are desirable.